Ultra-Low Power Asynchronous Processor Design

In an UAF-SPI collaboration, researchers are designing an innovative circuit architecture that will be highly tolerant to Single Event Upset (SEU) and Single Event Latchup (SEL) by using delay-insensitive asynchronous logic and advanced radiation tolerant packaging techniques. Furthermore, early work has revealed that similar asynchronous design can operate at very low temperatures (as low as 2K) and over a relatively broad thermal range. Compared to the existing SEU/SEL mitigation techniques, e.g., Silicon-on-Insulator (SOI), Triple Modular Redundancy (TMR), and Error Detection and Correction code (EDAC).

The proposed Double Modular Redundancy (DMR) technique is more cost efficient since it can be implemented using commercial CMOS fabrication process, and is more effective because it does not have vulnerability like the voter circuit in TMR and encoding/decoding circuits in EDAC. Moreover, the technique under development is able to retain the data being processed during the power cycling period for SEL mitigation, in contrast to the existing counterpart where data will be lost while mitigating SEL.

Performance Enhanced Managed FPGA (mFPGA)

The Performance Enhanced Managed Field Programmable Gate Array (mFPGA) is a system component that contains an FPGA, microprocessor, and security features, packaged within a multi-chip module that provides important services, such as dynamic partial reconfiguration, defragmentation, secure bitstream decryption, and security management.

These features make this enhanced FPGA a sustainable, upgradeable component for use in a wide variety of DoD applications. Innovations include the use of a microprocessor to manage the FPGA, perform full and partial reconfiguration, defragmentation, and security functions. The algorithms running on the microprocessor are implemented in C++, easing the upgrade and maintenance cycle as new techniques become available. Security features include basic key management, programmable decryption algorithms for bitstream security, and security management.

PCB Design Services
FPGA Core Design
Underside of FPGA

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Space Photonics Inc.

701 Research BLVD

72701 Fayetteville, AR

cchalfant@spacephotonics.com

(479) 466-7655